Methods of forming a conductive contact structure to a top electrode of an embedded memory device on an IC product and a corresponding IC product

ABSTRACT

One illustrative method disclosed herein includes, among other things, selectively forming a sacrificial material on an upper surface of a top electrode of a memory cell, forming at least one layer of insulating material around the sacrificial material and removing the sacrificial material so as to form an opening in the at least one layer of insulating material, wherein the opening exposes the upper surface of the top electrode. The method also includes forming an internal sidewall spacer within the opening in the at least one layer of insulating material and forming a conductive contact structure that is conductively coupled to the upper surface of the top electrode, wherein a portion of the conductive contact structure is surrounded by the internal sidewall spacer.

BACKGROUND OF THE INVENTION Field of the Invention

The present disclosure generally relates to the fabrication ofintegrated circuits, and, more particularly, to various novel methods offorming a conductive contact structure to a top electrode of an embeddedmemory device on an integrated circuit (IC) product and a correspondingIC product.

Description of the Related Art

In many modern integrated circuit products, embedded memory devices andlogic circuits (e.g., microprocessors) are formed on the same substrateor chip. Such embedded memory devices may come in a variety of forms,e.g., an MTJ (magnetic tunnel junction) memory device, an RRAM(resistive random access memory) device, a PRAM (phase-change randomaccess memory) device, an MRAM (magnetic random access memory) device, aFRAM (ferroelectric random access memory) device, etc. Typically, all ofthe embedded memory devices have a top electrode to which a conductivecontact structure must be formed for the device to be operational.

Various techniques have been employed to try to form such a conductivecontact structure to the top electrode of such a memory device.Typically, after the top electrode is formed, it is covered by a layerof insulating material. At some point later in the process flow, theupper surface of the top electrode must be exposed to allow forformation of the conductive contact structure. One technique involvesetching a trench into the layer of insulating material so as to exposeor “reveal” the top electrode. This necessitates that the bottom of thetrench extend past the upper surface of the top electrode. One problemwith this technique is that it typically requires that the top electrodebe made relatively thicker so as to provide an increased process windowand reduce the chances of the trench exposing other parts of the memorydevice, leading to the creation of an undesirable electrical short thatwould render the memory device inoperable. Another manufacturingtechnique that is commonly employed involves directly patterning (viamasking and etching) a via that is positioned and aligned so as toexpose the upper surface of the top electrode. One problem with thisapproach is the fact that, as device dimensions continue to shrink, itis very difficult to properly align the via such that it only exposes aportion of the upper surface of the top electrode. Any misalignment ofthe via relative to the top electrode can result in undesirable exposureof the sidewalls of the top electrode, which can also lead toundesirable electrical shorts and device inoperability. Additionally,these processing steps lead to higher manufacturing costs and requirethe use of additional masking layers.

The present disclosure is generally directed to various novel methods offorming a conductive contact structure to a top electrode of an embeddedmemory device on an integrated circuit (IC) product and a correspondingIC product that may at least reduce one or more of the problemsidentified above.

SUMMARY

The following presents a simplified summary of the invention in order toprovide a basic understanding of some aspects of the invention. Thissummary is not an exhaustive overview of the invention. It is notintended to identify key or critical elements of the invention or todelineate the scope of the invention. Its sole purpose is to presentsome concepts in a simplified form as a prelude to the more detaileddescription that is discussed later.

Generally, the present disclosure is directed to various novel methodsof forming a conductive contact structure to a top electrode of anembedded memory device on an IC product and an IC product having such anovel corresponding configuration. One illustrative method disclosedherein includes, among other things, performing a selective formationprocess to selectively form a sacrificial material on an upper surfaceof the top electrode, forming at least one layer of insulating materialaround the sacrificial material and removing the sacrificial material soas to form an opening in the at least one layer of insulating material,wherein the opening exposes the upper surface of the top electrode. Inthis illustrative example, the method also includes forming an internalsidewall spacer within the opening in the at least one layer ofinsulating material and forming a conductive contact structure that isconductively coupled to the upper surface of the top electrode, whereina portion of the conductive contact structure is surrounded by theinternal sidewall spacer.

One illustrative integrated circuit product disclosed herein includes amemory cell including a top electrode, an opening in at least one layerof insulating material, wherein the opening exposes at least a portionof an upper surface of the top electrode of the memory cell, and aninternal sidewall spacer positioned within the opening, wherein theinsulating material and the internal sidewall spacer are made ofdifferent materials. The product also includes a conductive contactstructure that is conductively coupled to the upper surface of the topelectrode, wherein a portion of the conductive contact structure issurrounded by the internal sidewall spacer.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure may be understood by reference to the followingdescription taken in conjunction with the accompanying drawings, inwhich like reference numerals identify like elements, and in which:

FIGS. 1-13 depict various novel methods of forming a conductive contactstructure to a top electrode of an embedded memory device on an ICproduct and an IC product having such a novel correspondingconfiguration.

While the subject matter disclosed herein is susceptible to variousmodifications and alternative forms, specific embodiments thereof havebeen shown by way of example in the drawings and are herein described indetail. It should be understood, however, that the description herein ofspecific embodiments is not intended to limit the invention to theparticular forms disclosed, but on the contrary, the intention is tocover all modifications, equivalents, and alternatives falling withinthe spirit and scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION

Various illustrative embodiments of the invention are described below.In the interest of clarity, not all features of an actual implementationare described in this specification. It will of course be appreciatedthat in the development of any such actual embodiment, numerousimplementation-specific decisions must be made to achieve thedevelopers' specific goals, such as compliance with system-related andbusiness-related constraints, which will vary from one implementation toanother. Moreover, it will be appreciated that such a development effortmight be complex and time-consuming, but would nevertheless be a routineundertaking for those of ordinary skill in the art having the benefit ofthis disclosure.

The present subject matter will now be described with reference to theattached figures. Various structures, systems and devices areschematically depicted in the drawings for purposes of explanation onlyand so as to not obscure the present disclosure with details that arewell known to those skilled in the art. Nevertheless, the attacheddrawings are included to describe and explain illustrative examples ofthe present disclosure. The words and phrases used herein should beunderstood and interpreted to have a meaning consistent with theunderstanding of those words and phrases by those skilled in therelevant art. No special definition of a term or phrase, i.e., adefinition that is different from the ordinary and customary meaning asunderstood by those skilled in the art, is intended to be implied byconsistent usage of the term or phrase herein. To the extent that a termor phrase is intended to have a special meaning, i.e., a meaning otherthan that understood by skilled artisans, such a special definition willbe expressly set forth in the specification in a definitional mannerthat directly and unequivocally provides the special definition for theterm or phrase.

As will be readily apparent to those skilled in the art upon a completereading of the present application, the presently disclosed method maybe applicable to a variety of products, including, but not limited to,logic products, memory products, etc. With reference to the attachedfigures, various illustrative embodiments of the methods and devicesdisclosed herein will now be described in more detail.

FIGS. 1-13 depict various novel methods of forming a conductive contactstructure to a top electrode of an embedded memory device on an ICproduct 100 and an IC product 100 having such a novel correspondingconfiguration. The IC product 100 will be formed on and above asemiconductor substrate (not shown). The semiconductor substrate mayhave a variety of configurations, such as a bulk silicon configuration.The substrate may also have a semiconductor-on-insulator (SOI)configuration that includes a base semiconductor layer, a buriedinsulation layer and an active semiconductor layer positioned above theburied insulation layer, wherein transistor devices (not shown) that areformed on the substrate are formed in and above the active semiconductorlayer. The substrate may be made of silicon or it may be made ofmaterials other than silicon. Thus, the terms “substrate” or“semiconductor substrate” should be understood to cover allsemiconducting materials and all forms of such materials. The variouscomponents, structures and layers of material depicted herein may beformed using a variety of different materials and by performing avariety of known process operations, e.g., chemical vapor deposition(CVD), atomic layer deposition (ALD), a thermal growth process,spin-coating techniques, etc. The thicknesses of these various layers ofmaterial may also vary depending upon the particular application.

In general, and with reference to FIG. 1, the IC product 100 comprises amemory region 102 where one or more memory devices will be formed and alogic region 104 where one or more logic circuits (e.g., microprocessorcircuits) will be formed in and above a semiconductor substrate (notshown in the attached figures). As is typical, the IC product 100includes a plurality of metallization layers that constitute the overallwiring pattern for the IC product 100. These metallization layers may beformed on the IC product 100 by performing traditional manufacturingprocesses. These metallization layers are typically comprised of layersof insulating material (e.g., silicon dioxide) with a plurality ofconductive metal lines and/or or conductive vias formed in the layers ofmaterial. The conductive metal lines are routed across the substrate invarious patterns and arrangements and provide the means for intra-layerelectrical communication between the devices and structures formed on orabove the substrate. The conductive vias provide the means for allowingelectrical communication between the conductive metal lines in adjacentmetallization layers. The first metallization layer of an IC product istypically referred to as the “M1” layer (or in some cases the “M0”layer), while the conductive vias that are used to establish electricalconnection between the M1 layer and the conductive lines in theimmediately adjacent upper metallization layer (the “M2 layer) aretypically referred to as “V1” vias. So-called device level contacts (notshown) are formed above the substrate so as to provide electricalcommunication between the various devices, e.g., transistors, resistors,etc., that are formed on or immediately adjacent the semiconductorsubstrate.

FIG. 1 depicts the IC product 100 after several process operations havebeen formed. More specifically, FIG. 1 depicts the product 100 at apoint in time wherein an illustrative (and representative) metallizationlayer 105 has been formed above a semiconductor substrate (not shown).As will be appreciated by those skilled in the art after a completereading of the present application, the metallization layer 105 isintended to be representative of any metallization layer that may beformed on the IC product irrespective of its location relative to anupper surface of the semiconductor substrate or any of the othermetallization layers formed on the IC product 100.

With continued reference to FIG. 1, the product 100 is depicted at apoint in time where a layer of insulating material 106, e.g., silicondioxide, for a representative metallization layer—M_(last)—of the ICproduct 100 has been formed above the semiconductor substrate. As notedabove the M_(last) metallization layer is intended to be representativeof any metallization layer formed at any level on the IC product 100. Inthe example shown in FIG. 1, various illustrative conductive metal lines108 have been formed in the layer of insulating material 106 in both thememory region 102 and the logic region 104. The number, size, shape,configuration and overall routing of the metal lines 108 may varydepending upon the particular application. In one example, theconductive metal lines 108 are elongated features that extend across theproduct 100 in a direction that is transverse to the plane of thedrawing in FIG. 1. The metal lines 108 may be comprised of any of avariety of different conductive materials, e.g., copper, aluminum,tungsten, etc., and they may be formed by traditional manufacturingtechniques, e.g., by performing a damascene process for cases where theconductive lines 108 are made of copper and perhaps by performingtraditional deposition and etching processes when the conductive lines108 are made of a conductive material that may readily be patternedusing traditional masking and patterning (e.g., etching) techniques.

Also depicted in FIG. 1 is an etch-stop layer 110 that was formed abovethe layer of insulating material 106. The etch-stop layer 110 may becomprised of a variety of different materials, e.g., silicon nitride,carbon-doped nitride (NDC), NBLK, advanced etch stop layers likeAlN/ODC, etc. The thickness of the etch-stop layer 110 may varydepending upon the particular application. Next, a layer of insulatingmaterial 112 was blanket-deposited above the etch-stop layer 110. Ifdesired, a planarization process may be performed on the layer ofinsulating material 112 to substantially planarize its upper surface.The layer of insulating material 112 may be comprised of a variety ofdifferent insulating materials, e.g., silicon dioxide, TEOS, ultra low-kmaterials, OMCTS, densified ULK, etc., and its vertical thickness mayvary depending upon the particular application.

Next, a first patterned etch mask (not shown) was formed on the product100. This particular patterned etch mask covers the logic region 104 butexposes portions of the layer of insulating material 112 at locations inthe memory region 102 where it is desired to establish electricalcontact with the conductive lines 108 formed in the layer of insulatingmaterial 106 within the memory region 102. At that point, a firstetching process may be performed through the first patterned etch mask(not shown) so as to remove exposed portions of the layer of insulatingmaterial 112 in the memory region 102. This etching process operationstops on the etch stop layer 110. Thereafter, a relatively brief etchingprocess may be performed to etch through the etch stop layer 110 so asto thereby form overall contact openings 111 that extend through thelayer of insulating material 112 and the etch-stop layer 110 and therebyexpose at least portion of the upper surface of the conductive lines 108in the memory region 102. At that point, the first patterned etch maskmay be removed. Then, a conductive via 114 is formed in the openings 111using traditional manufacturing processing techniques, e.g., byperforming a deposition process so as to overfill the openings 111 inthe memory region 102 with conductive material(s), followed byperforming a chemical mechanical planarization (CMP) process operationto remove the excess amounts of the conductive material for theconductive vias 114 that are positioned on or above the upper surface ofthe layer of insulating material 112. In one illustrative embodiment,when viewed from above, the conductive vias 114 may have a substantiallycircular configuration. In other situations, the conductive vias 114 mayhave a substantially oval configuration. The vertical thickness of theillustrative vias 114 may vary depending upon the particularapplication, and they may be comprised of a variety of conductivematerials, e.g., copper, tungsten, aluminum, etc. The conductive vias114 may be comprised of the same material of construction as that of theconductive metal line 108 to which it is conductively coupled, but thatmay not be the case in all applications. Of course, as will beappreciated by those skilled in the art after a complete reading of thepresent application, various barrier layers or liner layers (neither ofwhich is shown) may be formed as part of the process of forming theillustrative conductive lines 108 and the conductive vias 114. Moreover,various additional conductive structures that will be formed on the ICproduct 100, as discussed more fully below, may or may not include suchillustrative barrier layers and/or liner layers, which are not depictedso as to not overly complicate the attached drawings.

FIG. 2 depicts the IC product 100 after several process operations wereperformed. First, a second layer of insulating material 112 was formedon the product 100. For ease of reference, the reference numeral 112will be used to refer to all of the various layers of insulatingmaterial that will be formed on the product 100. Of course all of thelayers of insulating material need not be of the same material, e.g.,silicon dioxide, but that may be the case in some applications.Thereafter, a second patterned etch mask (not shown) was formed on theproduct 100 above the second layer of insulating material 112. Thesecond patterned etch mask covers the logic region 104 and exposesportions of the memory region 102 wherein it is desired to formconductive structures that will conductively contact the vias 114. Atthat point, an etching process may be performed through the secondpatterned etch mask (not shown) so as to form openings 113 in the secondlayer of insulating material 112 in the memory region 102. The formationof the openings 113 exposes the upper surface of the conductive vias114. Then, the second patterned etch mask was removed. Next, a layer ofconductive material 116 was formed in both the memory region 102 and thelogic region 104. As depicted, the conductive material 116 overfills theopenings 113 in the second layer of insulating material 112 in thememory region 102. In the depicted example, a CMP process may beperformed to remove some of the conductive material 116 positioned abovethe memory region 102 and the logic region 104, while leaving arelatively thin layer of the conductive material 116 positioned abovethe second layer of insulating material 112 in both the memory region102 and the contact region 104. In other applications, a CMP process maybe performed to remove all of the conductive layer 116 positioned abovethe upper surface of the layer of insulating material 112 in both thememory region 102 and the logic region 104, thereby leaving theconductive material 116 only in the openings 113 in the second layer ofinsulating material 112 in the memory region 102. In yet otherapplications, after removing the conductive material everywhere outsideof the openings 113, additional conductive material 116 may be depositedon the product followed by performing a CMP process. In one illustrativeembodiment, when viewed from above, the portion of the conductivematerial 116 within the opening 113 may have a substantially circularconfiguration. In other situations, the conductive material 116 withinthe opening 113 may have a substantially oval configuration. The layerof conductive material 116 may be formed to any desired thickness and itmay comprise any conductive material, e.g., copper, tungsten, ruthenium,aluminum, TaN, etc.

Next, with reference to FIGS. 2 and 3, one or more layers of memorystate material 118 was formed above the product 100 in both the memoryregion 102 and the logic region 104. As will be appreciated by thoseskilled in the art after a complete reading of the present application,the present disclosure is directed to the formation of a conductivecontact to a top electrode of an embedded memory cell 122 (see FIG. 3)on the IC product etch stop layer 110. The memory cell 122 depictedherein is intended to be generic and representative in nature. By way ofexample only, and not by way of limitation, the generic memory cells 122depicted herein may take a variety of forms, have a variety of differentconfigurations and may comprise different materials. For example, thememory cells 122 depicted herein may be an MTJ (magnetic tunneljunction) memory device, an RRAM (resistive random access memory)device, a PRAM (phase-change random access memory) device, an MRAM(magnetic random access memory) device, a FRAM (ferroelectric randomaccess memory) device, etc. Such a memory cell 122 includes some form ofmemory state material 118 that is typically positioned between a bottomelectrode and a top electrode. In some applications, some characteristicof the memory state material 118, e.g., resistivity, may be altered bythe application of an electrical charge to the memory device 122, andthese altered states may be representative of a logical “1” or a logical“0” in a digital circuit. In some situations, the memory state material118 may actually store an electrical charge. In any event, sensingcircuitry on the IC product 100 may be used to sense the state of thememory state material 118, to determine whether or not a particularmemory cell 122 represents a logical “1” or a logical “0” and use thatinformation within the various circuits on the IC product 100. Theparticular materials used for the memory state material 118 may varydepending upon the particular type of memory device that is fabricated.Moreover, the single layer of memory state material 118 depicted in thedrawings is intended to be representative in that, in a real-worlddevice, the memory state material 118 may comprise a plurality of layersof material. Thus, the reference to any “memory state material” in thespecification and in the attached claims should be understood to coverany form of any material(s) that may be employed on any form of a memorydevice that can be manipulated or changed so as to reflect two oppositelogical states of the memory device.

Still with reference to FIG. 2, after formation of the memory statematerial 118, another layer of conductive material 120 was formed on theproduct 100 in both the memory region 102 and the logic region 104. Thelayer of conductive material 120 may be formed to any desired thicknessand it may comprise any conductive material, such as those listed abovefor the layer of conductive material 116. In some applications, thelayer of conductive material 116 and the layer of conductive material120 may be made of the same material, but that may not be the case inall applications.

FIG. 3 depicts the product 100 after several process operations wereperformed. First, a patterned etch mask (not shown) was formed above theproduct 100. The patterned etch mask exposes the logic region 104 whilecovering portions of the memory region 102. Thereafter, one or moreetching processes were performed to remove the exposed portions of thelayer of conductive material 120, the memory state material 118 and thelayer of conductive material 116. Thereafter, the patterned etch maskwas removed. As depicted, this process results in the formation of twoillustrative memory cells 122 in the memory section 102. Each of thememory cells 122 comprises a top electrode 120A, a bottom electrode 116Aand a portion of the memory state material 118 positioned between thosetwo electrodes.

FIG. 4 depicts the product after a third layer of insulating material112 was formed on the product 100 and after a planarization process (CMPor etch-back) was performed. As a result, the upper surface of the topelectrode 120A of each of the memory cells 122 is exposed.

FIG. 5 depicts the product 100 after a selective deposition process wasperformed to form a sacrificial material 124 only on the exposed uppersurface of each of the top electrodes 120A. In one illustrativeembodiment, the sacrificial material 124 may be a self-assembledmaterial (SAM) or it may be a selectively grown metal material such ascobalt, etc. The sacrificial material 124 may be formed to any desiredthickness.

FIG. 6 depicts the product after a fourth layer of insulating material112 was formed on the product 100 and after a planarization process (CMPor etch-back) was performed. As a result, the upper surface of thesacrificial material 124 above the top electrode 120A of each of thememory cells 122 is exposed.

FIG. 7 depicts the product 100 after an etching process was performed toselectively remove the sacrificial material 124 relative to thesurrounding materials. This results in the formation of openings 112X inthe fourth layer of insulating material 112 and exposes the uppersurface of each of the top electrodes 120A.

FIG. 8 depicts the IC product 100 after a conformal deposition processwas performed to form a conformal layer of spacer material 126 acrossthe product 100. The layer of spacer material 126 may be of any desiredthickness and it may be comprised of any material that providessignificant etch selectivity relative to the material of the fourthlayer of insulating material 112 and the top electrode 120A. Forexample, in one illustrative embodiment, where the fourth layer ofinsulating material 112 is silicon dioxide, the layer of spacer material126 may be made of silicon nitride. Of course, the layer of spacermaterial 126 may be made of a variety of different materials dependingupon the particular application and the material of the fourth layer ofinsulating material 112, e.g., silicon dioxide, a low-k material,silicon nitride, SiCN, SiN, SiCO, and SiOCN, etc.

FIG. 9 depicts the product 100 after an anisotropic etching process wasperformed to remove horizontally positioned portions of the layer ofspacer material 126. This etching process results in the formation of aninternal sidewall spacer 126A in each of the openings 112X in the fourthlayer of insulating material 112. The spacers 126A may be of any desiredthickness (as measured at their base). This process operation alsore-exposes the upper surface of the top electrode 120A that is notcovered by the internal spacer 126A.

FIG. 10 depicts the product after a fifth layer of insulating material112 was formed on the product 100 and after a planarization process (CMPor etch-back) was performed. The additional insulation material from thefifth layer of insulating material 112 overfills the portions of theopening 112X that are not filled by the internal sidewall spacer 126A.At the point of processing depicted in FIG. 10, various processoperations may be performed to form various contact openings in thevarious layers of insulating material for various conductive contactstructures that will conductively contact the top electrode 120A of eachof the memory cells as well as a conductive contact structure that willconductively contact the metal line 108 in the logic regions. As will beappreciated by those skilled in the art after a complete reading of thepresent application, there are several possible process flows forforming such conductive contacts. FIGS. 11-13 depict one suchillustrative process flow that employs a via first, trench lasttechnique.

FIG. 11 depicts the process after a patterned etch mask (not shown) wasformed above the product 100. The patterned etch mask covers the memoryregion 102 and exposes a portion of the logic region 104. Thereafter, atleast one etching process was performed to form a via portion 128 of acontact opening in the logic region 104. The via 128 stops on the etchstop layer 110. After the via 128 is formed in the logic region 104, thepatterned etch mask may be removed.

FIG. 12 depicts the product 100 after another patterned etch mask (notshown) was formed above the product 100. This patterned etch maskexposes portions of both the memory region 102 and the logic region 104.Thereafter, at least one etching process was performed to form trenches130 (i.e., contact openings) in the memory region 102 and to form atrench portion 133 of the contact opening in the logic region 104. Inone illustrative process flow, after formation of the trench 133, aseparate “punch-through” etching process may need to be performed toremove portions of the etch stop layer 110 positioned above theconductive line 108 in the logic region 104. Thereafter, the patternedetch mask may be removed. Note that the sidewall spacer 126A is made ofa material that also exhibits good etch selectivity relative to thefifth layer of insulating material 112 as the sidewall spacers 126Aremain intact during the process of etching the trenches 130. Asdepicted, the formation of the trenches 130 exposes the upper surface ofthe top electrodes 120A. Note that, due to the presence of the internalsidewall spacer 126A, the formation of the lower portion of the trenches130 is essentially a self-aligned process. That is, in the illustrativeexample depicted in the enlarged section in the dashed line oval regionshown in FIG. 12, a portion of the trench 130 stops on the upper surface126X of the internal spacer 126A. In one illustrative embodiment, thisetching process removes substantially all of the insulating materialpositioned within the interior of the internal sidewall spacer 126A. Inthe example depicted in the enlarged section, the trench 130 issubstantially perfectly aligned with the internal spacer 126A. Ofcourse, in a real-world device, the trench 130 may be laterally offsetfrom the idealized position depicted in FIG. 12. Additionally, thelateral width of the sidewall spacer 126A may be increased so as toprovide a larger process window with respect to the alignment of thetrench 130 relative to the top electrode 120A. Since the sidewall spacer126A will also be exposed to the above-mentioned punch-through etchingprocess, the sidewall spacer 126A will need to exhibit good etchselectivity relative to the material of the etch stop layer 110.

FIG. 13 depicts the product 100 after various process operations wereperformed to form conductive contact structures 134 and a conductivecontact structure 136 in the contact openings. Each of the conductivecontact structures 134 is conductively coupled to the top electrode 120Aof one of the memory cells 122. The conductive contact structure 136 isconductively coupled to the metal line 108 in the logic region 104.Given that, in some embodiments, a portion of the trench 130 stops onthe upper surface 126X of the internal spacer 126A, it follows that aportion of the conductive contact structure 134 will also engage atleast a portion of the upper surface 126X of the internal sidewallspacer 126A. FIG. 13 also contains a cross-sectional view taken at thelocation of the dashed line in the figure. As depicted, the internalspacer 126A surrounds the portion of the conductive contact structure134 that is positioned within the spacer 126A. In one illustrativeexample, the portion of the conductive contact structure 134 positionedwithin the internal spacer 126A contacts and engages the entire internalperimeter of the internal sidewall spacer 126A. The conductive contactstructures 134, 136 may be formed using a variety of techniques. In oneexample, various conformal liners and/or barrier layers may be formed inthe trench/via openings. Thereafter, a conductive material, such astungsten, may be deposited so as to overfill the remaining portions ofthe trench/via openings. At that point, a CMP process operation may beperformed to remove all conductive material positioned above the uppersurface of the fifth layer of insulating material 112.

The particular embodiments disclosed above are illustrative only, as theinvention may be modified and practiced in different but equivalentmanners apparent to those skilled in the art having the benefit of theteachings herein. For example, the process steps set forth above may beperformed in a different order. Furthermore, no limitations are intendedto the details of construction or design herein shown, other than asdescribed in the claims below. It is therefore evident that theparticular embodiments disclosed above may be altered or modified andall such variations are considered within the scope and spirit of theinvention. Note that the use of terms, such as “first,” “second,”“third” or “fourth” to describe various processes or structures in thisspecification and in the attached claims is only used as a shorthandreference to such steps/structures and does not necessarily imply thatsuch steps/structures are performed/formed in that ordered sequence. Ofcourse, depending upon the exact claim language, an ordered sequence ofsuch processes may or may not be required. Accordingly, the protectionsought herein is as set forth in the claims below.

The invention claimed is:
 1. A method of forming a conductive contactstructure to a top electrode of a memory device, the method comprising:forming a first layer of insulating material adjacent and in physicalcontact with a side surface of the top electrode of the memory device;forming a second layer of insulating material above the first layer ofinsulating material; forming an opening in the second layer ofinsulating material, the opening exposing an upper surface of the topelectrode; forming an internal sidewall spacer within the opening in thesecond layer of insulating material; forming a third layer of insulatingmaterial above the second layer of insulating material; and forming aconductive contact structure that is conductively coupled to the uppersurface of the top electrode, wherein the conductive contact structureincludes a first portion that is surrounded by the internal sidewallspacer, and a second portion that is surrounded by and in physicalcontact with at least a portion of the third layer of insulatingmaterial, wherein the first portion of the conductive contact structuresurrounded by the internal sidewall spacer is in physical contact withan entire internal perimeter of the internal sidewall spacer such thatthe entire internal perimeter of the internal sidewall spacer enclosesthe first portion of the conductive contact structure.
 2. The method ofclaim 1, wherein forming the internal sidewall spacer comprises: forminga conformal layer of a spacer material above the second layer ofinsulating material and in the opening; and forming the internalsidewall spacer within the opening from a portion of the conformed layerof the spacer material.
 3. The method of claim 1, wherein, prior toforming the conductive contact structure, the method comprises: formingadditional insulation material above the second layer of insulatingmaterial, the additional insulation material filling a remaining portionof the opening in the second layer of insulating material that is notoccupied by the internal sidewall spacer; and forming at least a portionof a contact opening in the additional insulating material to expose atleast a portion of the upper surface of the top electrode.
 4. The methodof claim 3, wherein the portion of the contact opening within theinternal sidewall spacer is formed in a self-aligned manner.
 5. Themethod of claim 3, wherein at least a portion of the contact openingabuts an upper surface of the internal sidewall spacer.
 6. An integratedcircuit product, comprising: a memory cell comprising a top electrode; afirst layer of insulating material adjacent and in physical contact witha side surface of the top electrode, a second layer of insulatingmaterial above the first layer of insulating material; an opening in thesecond layer of insulating material, the opening exposing at least aportion of an upper surface of the top electrode; an internal sidewallspacer positioned within the opening in the second layer of insulatingmaterial; a third layer of insulating material above the second layer ofinsulating material; and a conductive contact structure that isconductively coupled to the upper surface of the top electrode, whereinthe conductive contact structure includes a first portion that issurrounded by the internal sidewall spacer, and a second portion that issurrounded by and in physical contact with at least a portion of thethird layer of insulating material, wherein the first portion of theconductive contact structure surrounded by the internal sidewall spaceris in physical contact with an entire internal perimeter of the internalsidewall spacer such that the entire internal perimeter of the internalsidewall spacer encloses the first portion of the conductive contactstructure.
 7. The integrated circuit of claim 6, wherein at least aportion of the conductive contact structure abuts an upper surface ofthe internal sidewall spacer.
 8. The integrated circuit of claim 6,wherein an upper surface of the internal sidewall spacer abuts both atleast a portion of the third layer of insulating material and at least aportion of the conductive contact structure.
 9. The integrated circuitof claim 6, wherein one or more of the first, the second, and the thirdlayers of insulating material includes a first material, and wherein theinternal sidewall spacer includes a second material that is differentfrom the first material.
 10. The integrated circuit of claim 6, whereinone or more of the first, the second, and the third layers of insulatingmaterial includes silicon dioxide, the internal sidewall spacer includessilicon nitride and the memory cell includes an MTJ (magnetic tunneljunction) memory device, an RRAM (resistive random access memory)device, a PRAM (phase-change random access memory) device, an MRAM(magnetic random access memory) device, or a FRAM (ferroelectric randomaccess memory) device.
 11. The integrated circuit of claim 6, whereinthe internal sidewall spacer further includes an upper surface thatabuts both a portion of the third layer of insulating material and aportion of the conductive contact structure.
 12. The method of claim 1,wherein one or more of the first, second, and the third layers ofinsulating material comprises silicon dioxide, the internal sidewallspacer comprises silicon nitride and the memory device comprises one ofan MTJ (magnetic tunnel junction) memory device, an RRAM (resistiverandom access memory) device, a PRAM (phase-change random access memory)device, an MRAM (magnetic random access memory) device, or a FRAM(ferroelectric random access memory) device.
 13. The method of claim 1,wherein an upper surface of the internal sidewall spacer furtherincludes an upper surface that abuts both a portion of the third layerof insulating material and a portion of the conductive contactstructure.